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SN74LVC2G74YZPR CP7 的参数 |
| 功能
Function |
设置（预设）和复位 Set(Preset) and Reset |
| 类型
Type |
D型 D-Type |
| 输出类型
Output Type |
差分 Differential |
| 元件数
Number of Elements |
1 |
| 每元件位数
Number of Bits per Element |
1 |
| 时钟频率
Frequency - Clock |
200MHz |
| 传播延迟时间
Delay Time - Propagation |
4.1ns |
|
正边沿 Positive Edge |
| 触发器类型
Trigger Type |
32mA，32mA |
| 输出高电平，低电平电流
Current - Output High, Low |
1.65 V ~ 5.5 V |
| 电源电压
Voltage - Supply |
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET DESCRIPTION/ORDERING INFORMATION SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES203M–APRIL 1999–REVISED FEBRUARY 2007 ? Available in the Texas Instruments ? Typical VOHV (Output VOH Undershoot) NanoFree? Package >2 V at VCC = 3.3 V, TA = 25°C ? Supports 5-V VCC Operation ? I off Supports Partial-Power-Down Mode ? Inputs Accept Voltages to 5.5 V Operation ? Latch-Up Performance Exceeds 100 mA Per ? Max t pd of 5.9 ns at 3.3 V JESD 78, Class II ? Low Power Consumption, 10-μA Max ICC ? ESD Protection Exceeds JESD 22 ? ±24-mA Output Drive at 3.3 V – 2000-V Human-Body Model (A114-A) ? Typical VOLP (Output Ground Bounce) <0.8 V at V – 200-V Machine Model (A115-A) CC= 3.3 V, TA= 25°C – 1000-V Charged-Device Model (C101) This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. NanoFree? package technology is a major breakthrough in IC packaging concepts, using the die as the package. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using I off The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. "Available in the Texas Instruments ? Typical VOHV (Output VOH Undershoot) NanoFree? Package >2 V at VCC = 3.3 V, TA = 25°C ? Supports 5-V VCC Operation ? I off Supports Partial-Power-Down Mode ? Inputs Accept Voltages to 5.5 V Operation ? Latch-Up Performance Exceeds 100 mA Per ? Max tpd of 5.9 ns at 3.3 VJESD 78, Class II ? Low Power Consumption, 10-μA Max ICC ? ESD Protection Exceeds JESD 22 ? ±24-mA Output Drive at 3.3 V – 2000-V Human-Body Model (A114-A) ? Typical VOLP (Output Ground Bounce) <0.8 V at V – 200-V Machine Model (A115-A) CC= 3.3 V, TA= 25°C 1000-V Charged-Device Model (C101)" |
| Description & Applications |
单正边沿触发的D-型触发器 具有清零和预设 描述/订购信息 SN74LVC2G74 单正边沿触发的D-型触发器 具有清零和预设 1999年4月SCES203M REVISED2007年2月 ?德州仪器典型VOHV （输出VOH冲） NanoFree?封装>2 V在VCC=3.3 V，TA= 25°C ?支持5-V VCC操作?我 关闭支持部分掉电模式 ?输入接受5.5 V操作电压 ?闭锁性能超过100 mA每 ?最大t PD为5.9 ns在3.3 V JESD 78，II类 ?低功耗，10μA最大I CC ?ESD保护超过JESD22 ?±24 mA输出驱动在3.3 V - 2000-V人体模型（A114-A） ?典型的VoIP （输出地弹跳） 在V<0.8 V - 200-V机型号（A115-A） CC=3.3 V，TA = 25°C - 1000-V带电器件模型（C101） 这种单一的正边沿触发D型触发器是专为1.65-V到5.5 V的VCC操作。 NanoFree包装技术是IC包装概念的重大突破，使用的模具 包。 在低水平预设（PRE）或清除（CLR）输入设置或复位输出，无论水平 其他投入。当PRE和CLR无效（高），数据在数据输入（D）会议的设置时间 要求转移到输出的时钟脉冲上的正边沿。时钟触发发生 在电压等级，并没有直接关系，在时钟脉冲的上升时间。保持时间间隔之后， D输入的数据可以改变，而不影响产出水平。 这个装置是完全指定部分断电应用程序使用I 离。的I 关闭电路禁止输出， 防止损坏电流回流通过设备时，断电。 可用的在得克萨斯州仪器?典型的VOHV （输出VOH冲） NanoFree?封装>2 V在VCC=3.3 V，TA= 25°C ?支持5-V VCC操作?我 关闭支持部分掉电模式 ?输入接受5.5 V操作电压 ?闭锁性能超过100 mA每 ?最大TPD为5.9 ns3.3 VJESD78，II类 ?低功耗，10μA最大ICC ?ESD保护超过JESD22 ?±24 mA输出驱动在3.3 V - 2000-V人体模型（A114-A） ?典型的VoIP （输出地弹跳） 在V<0.8 V - 200-V机型号（A115-A） CC = 3.3 V，TA= 25°C 1000-V带电器件模型（C101） |
| 描述与应用 |
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| 技术文档PDF下载 |
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相关型号列表 |
| 型号 |
标记/丝印/代码 |
厂家 |
批号 |
封装 |
数量 |
描述 |
详细资料 |
| SN74LVC2G74DCTR-1 |
C74 |
TEXAS |
05+ |
SOT-183/DCT8 |
0 |
集成电路ICIntegrated Circuit（IC）-逻辑电路Logic circuit-触发器Flip Flops |
查看 |
| SN74LVC2G74DCUR |
C74R |
TEXAS |
05+ |
DSBGA |
0 |
集成电路ICIntegrated Circuit（IC）-逻辑电路Logic circuit-触发器Flip Flops |
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| SN74LVC2G74YZPR |
CP7 |
TEXAS |
0427+ROHS |
DSBGA |
1500 |
集成电路ICIntegrated Circuit（IC）-逻辑电路Logic circuit-触发器Flip Flops |
查看 |
| SN74LVC2G74YZPR |
CP7 |
TEXAS |
07nopb |
DSBGA |
4100 |
集成电路ICIntegrated Circuit（IC）-逻辑电路Logic circuit-触发器Flip Flops |
查看 |
| SN74LVC2G74DCTR-1 |
C74 |
TEXAS |
05+ |
SOT-183/DCT8 |
0 |
集成电路ICIntegrated Circuit（IC）-逻辑电路Logic circuit-触发器Flip Flops |
查看 |
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